1. Field of the Invention
The present invention is related to a method of erasing a NAND flash memory device and particularly, to a method of erasing which is able to improve a protecting function for erasing disturbance fails.
2. Discussion of Related Art
Data stored in a NAND flash memory device is erased in the unit of block. During this, there is no disturbance because a non-erased block is boosted such that a wordline of memory cells is supplied with 20V that is offset with a well bias 20V.
However, when a high voltage transistor employed in an X-decoder is conditioned in an abnormal state, a leakage current is generated and increases up to several tens through hundreds pA/μm. As a result, the bias voltage of 20V boosted at a gate of a non-erased memory cell decreases under 13V, so that information stored in the memory cell is lost due to disturbance by an erasing bias voltage of 20V set in a sell of a memory cell array.
FIG. 1 is a schematic diagram illustrating a conventional problem.
Referring to FIG. 1, while a gate of a non-selected memory cell A is required to be boosted and conditioned on 20V, there is a voltage drop due to a leakage current arising from a high voltage NMOS transistor B used as a selection transistor. Such a leakage current is generated from various reasons. Especially, a junction region of the high voltage NMOS transistor highly acts as the source of the leakage current (refer to the region L shown in FIG. 1).
Therefore, when the leakage current makes a voltage boosted for a control gate of a memory cell down more than 7V from its original voltage level, it causes a disturbance effect in a deselected cell block and then results in a serious problem that memory cells to be programmed are undesirably forced to be erased.